As background for our invention we will review some IBM Technical Disclosure Bulletins, so that the reader can more quickly follow our discussion and understand how our invention differs from prior art. Initially, it will be understood that our invention provides a prediction mechanism for detecting destructive storage operand overlap for MVC and instructions that can have operands that potentially overlap in a like manner to the MVC instruction. The invention is applicable to predicting destructive operand overlap for address calculations of the type used in the ESA/390 processor architecture. That it can be easily extended to support other architecture addressing modes is demonstrated by expanding the detection to include an assumed 64 bit addressing mode.
International Business Machines Corporation publishes a Technical Disclosure Bulletin, known as the TDB, about inventions made in IBM for public information. Turning now to the TDBs in this ad, we note that Ngai et al in TDB 12-82, Vol. 25, No. 7A, pp. 3569-3576, publish a fast algorithm for handling destructive operand overlap move instruction execution. The algorithm is suitable for MOVE CHARACTER, MOVE NUMERICS, and MOVE ZONES instruction types. The determination of the destructive operand overlap condition; however, is assumed and is not specified. The prediction of this assumed condition, on the other hand, is the subject of our invention.
Beetcher et al in TDB 06-81, Vol. 24, No. 1A, pp. 192-197, define a Move Long Embellished (MLE) instruction in which the behavior of the instruction depends on whether operands are overlapped. The instruction definition is specified in their TDB; however, the mechanism for detecting storage operand overlap is not defined.
Ngai et al in TDB 06-76 Vol. 19, No. 1, pp. 61-64, publish a hardware mechanism for determining destructive storage operand overlap by using bits of the destination address and source address to access a read only storage ("ROS") which at each memory location contains an indicator as to whether storage operand overlap may occur from the combination (over-indication). All bits of the address are used. No explaination for supporting multiple addressing modes is provided. In addition, their method determines whether the condition exists for the dataflow width of the machine. In our invention, we predict precisely whether storage operands possess destructive operand overlap as indicated by the architecture. The condition is generated if any byte within the operands overlap. Trace analysis indicate that conditions for which operands overlap with the operand length being less than storage data bus widths of a doubleword commonly found in current high performance processor implementations is infrequent; therefore, little performance is lost by detecting overlap for the general case. In any case, our indication is precise and not an over-indication. Secondly, we detect the condition totally with logic and do not rely upon an array access. Therefore, our determination should be faster and more cell efficient than the published mechanism. Finally, the published mechanism does not predict the overlap condition from bases, displacements and operand length as we do, but from the address after they are generated.
Brooks in TDB 06-76 Vol. 19, No. 1, pp. 222-224, published an operand consistency attendent (OCA) to prevent simultaneous, incompatible accesses to data fields. The hardware mechanism described determines if the operands overlap by comparing beginning and ending operand addresses. As such, not only are operand beginning address calculated prior to the determination, but also ending addresses. A mechanism for speeding up the comparisons once these beginning and ending addresses are available that approximates that the operands overlap is presented. We, on the other hand, determine the storage operand overlap condition in parallel with the generation of the source and destination addresses (beginning addresses for the TDB). In addition, our indication is precise.
Baker et al in TDB 01-82 Vol. 24, No. 8, pp. 4018-4022, published algorithms for executing many instructions whose behavior is architected, when operands overlap, to proceed as if the operands were processed byte by byte. It is assumed that the detection of operand overlap is already known and the algorithm for the executions are then provided. No mechanism is shown for detecting the operand overlap condition which is the subject of our invention.